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	Here is a brief outline of the vision project as it stands now.  I
have also enclosed a few block diagrams and some of the preliminary drawings.
These drawings are not done,  and may not used.  They are included just as
a guide for the outline.  The present plans for the whole system use between
100 and 130 I.C.s.  This number includes the 68000 system and all memory.
As a separate unit,  the preprocessor could be put on a 9 by 14 inch card.



   Prototype discription.

	The prototype will have four main parts:  video preprocessor and
shared memory,  sockets for the 68000 system and stand alone program memory,
I/O, and a 68000 evaluation board interface.  Programs will be developed in
RAM on the evaluation board and when debugged,  the 68000 and the program
memory would be inserted in the prototype and the evaluation board interface
removed.  Choice of a bus structure for the 68000 can be easily changed at
the system/preprocessor interface.

	The shared memory is the main link from the preprocessor to the 68000.
It will be consist of fast large RAMs arranged as two 16k by 8 bit blocks to
allow for byte addressing.  In a small system,  this is all the RAM that will
be needed for the 68000.

	The preprocessor micro word will range from 24 to 48 bits wide
depending on the number of different operations performed in parallel and the
functions needed.  The micro code will be RAM based and loaded on reset from
the 68000.  The design will provide for easy changing or expanding the micro
instruction set.  The micro program counter will be 12 bits wide with only 10
bits initialy implemented for a micro program size of 1k.  This is also easy to
expand.  The micro command register on the 68000 bus which is used to load the
micro code,  will double as the macro command register for the preprocessor.

	The prototype will be wired with two RS 232 serial I/O ports and two
DRV-11 compatible 16 bit parallel ports.  These will be easy to delete or
expand for different versions.  Since we feel that the main display I/O should
be a separate unit,  one parallel port can be dedicated for display and switch
I/O functions for a complete system.

	
	Initial preprocessor software will be simple run length encoding and
pixel summing on a binary picture within a programable window with the results
returned in the shared memory for the 68000.  This simple software could then
be expanded to include:  blob and hole area,  perimeter data,  first moments,
inclusion relations,  and simple shape and size information.  Data formats
would be designed for compatability with formats used in the 68000 based SRI
type module developed in the east.

	The design of the software and hardware will allow software and other
modules developed for the 68000 based SRI type system to be upgraded with
only minor modifications.  Although all of the capabilities of the new system
may not be needed for present applications,  by designing for expansion now we will
have the preformance needed for other applications.


   Preprocessor operation.


	Operation of the video interface starts with the selection of a camera
and an input gain.  Then the clock unit synchronizes to the camera timing and
triggers the flash,  if needed.  The selected video signal is then converted
to 4 bit pixel nibbles by each PCLK pulse.  Each nibble is then mapped with
the 16 by 4 bit RAM for background control and the number of bits per pixel.

	The output of the mapping RAM is the pixel data which is written into
the pixel buffer.  Depending on the number of pixels per picture and the number
of bits per pixel,  this buffer will range in size from 16k to 256k bits.
This memory consists of 1 to 16 16k dynamic RAMs which are refreshed by the
preprocessor.

	The address and format of the pixel buffer is controled by the 2942 DMA
counter and the DA register multiplexed on the DA bus.  The mapping RAM and
gating on the memory select lines provide for multiple pictures in the buffer
at the same time.  Refresh and cycle times of cheap 16k dynamic RAMS may require
interleaving the least significant address bit or even organizing the RAM with
byte wide data paths for high speed cameras.

	After all the pixels are written in the buffer,  the preprocessor scans
the picture one line at a time.  Each line is run length encoded and used to
generate the basic blob lists in the shared memory.  The preprocessor signals
the 68000 through the shared memory as each blob list and picture is finished.

	When the preprocessor is done scaning the picture,  it is free to
start taking another picture and process it while the 68000 works with the
basic blob lists.  Using a seperate pixel buffer allows for pipelined parallel
operation at a reasonable memory bandwidth.


   Project timetable.

	This timetable assumes that there are no big delays for wire wrap,
getting the parts,  development system,  etc..  Also,  wire wrap and debug
time must be allowed for if two boards are built unless they are both done
at once.


	4  weeks	Finish hardware design and wire wrap list generation.

	2  weeks	Wire wrap service,  writing development system interface
			software,  test software,  and macros for assembling the
			micro code.

	1  week		Wire wrap testing,  board stuffing,  making interface
			connectors, etc.

	4  weeks 	Debug,  test,  and modify hardware and low level
			software.

	5  weeks	Writing micro code for minimum SRI type system.

total  16  weeks


	After 10 to 12 weeks ( after all hardware is debuged ),  a second board
could be sent to the east for evaluation if they both were wired a the same
time,  or the second board could be started then and finished in time for the
software.